There are numerous circuits and structures known to the prior art as read-only memories. One such read-only memory may be generally described as follows:
The memory employs an array of storage cells having m columns and n rows. Each storage cell includes a transistor having a collector, base and emitter. The m.times.n array of transistors have a common collector and are formed in a single isolation region. During manufacture of the array each emitter of a transistor is either connected, or not, to its appropriate emitter rail according to a particular desired binary bit pattern. Information is then determined during the read out of the storage device by sensing whether or not current flows through a particular device at the intersection of two selected base and emitter rails.
The following U.S. Patents and publications are set-forth as representative of the prior art. It is to be appreciated that the art identified below is not all of the prior art or necessarily the best prior art.